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Wafer Level Packaging
3DIC is our most recent R&D focus. By taking advantage of our packaging expertise and experiences, we expanded our service from conventional assembling, which packages individual dies after wafer dicing, to wafer level packaging.
A 3DIC package includes 3 major components:
- Frontside Bump made of Cu/Ni/Au
- Through Silicon Via (TSV) including Via Middle and Via Last
- Backside Bump made of Cu/Ni/SnAg
Expanding from the core 3DIC structure, we further developed complementary technology:
- Cu/Ni/Au Redistribution Layer (RDL) in Cu or Au Wire Bonding Application
- Cu/(Ni)/SnAg Copper Pillar for Flip Chip Packages
- Through Silicon Via (TSV) used in 3DIC, Memory Cube, CMOS Image Sensor (CIS) TSV including CISCSP and CISCoW
Wafer Level Packages Choices:
- Cu Pillar Bump
- Lead-free Bump
- Redistribution Layer (RDL)
- 3DIC Packaging
- CMOS Image Sensor TSV
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