Through Silicon Via (TSV)
3D (Active TSV die) : Mobile and computing
2.5D (TSI, passive Si-Interposer):
Homogenous (DRAM or Logic only in FPGA), networking infrastructure
Heterogeneous (DRAM+ Logic): Gaming, HPC
Our solution in 3D IC offers Through Silicon Via (TSV) Via Middle, Via Last and memory cube die stacking.
For Via Middle (VM) process, IDM/Foundry will perform FEOL (CMOS), TSV formation
and metallization, we will perform via reveal and micro-bump (MEOL- Middle end
of line), die stacking or SiP/WLCSP. (BEOL- back end of line).
For Via Last (VL) process, IDM/Foundry will perform FEOL (CMOS) and
metallization, we will perform TSV formation, via reveal and micro-bump (MEOL),
die stacking or SiP/WLCSP (BEOL).
• TSV VL aspect ratio >3 TSV pitch 35um
• Si thickness 35um
• Backside organic and inorganic Passivation
For more information, please contact PTI Sales Office