CIS (CMOS Image Sensor) TSV

We provide Chip Scale Package (CSP) and Chip on Wafer (CoW) for packaging CMOS image sensors. Our package solution is available for both Front Side Illumination (FSI) and Back Side Illumination (BSI) wafers


To construct CIS CSP and CoW packages, our process includes the following stages:
- Dam Processing
- Glass Bonding
- TSV Etching and Formation.
- RDL Process
- Copper Pillar Bump Process (CPB)
- Solder Ball Mount Process
- Chip to Wafer Bonding
- Backend Dicing and Assembly Process

Chip Imaging Sensor Applications
- Video Terminal Adaptor.
- Play Station.
- Mobile Videophone.
- Virtual Keyboard.
- Digital Pen with Camera.
- Intelligent Parking Assist.
- IR Night Vision

CMOS Image Sensor (CIS) Chip Scale Packaging (CSP)
- Video Terminal Adaptor.
- 400 um glass, 120~180 °C bonding
- 45 um dam, 180 °C curing
- 100 um die thickness
- 40~70 um TSV diameter
- Aspect ratio 2.5 is achievable
- Less than 200°C CVD Oxide
- Stop Layer can be AL(CIS), Cu(CIS)


CIS CoW (TV2, Chip on Wafer)

In the CIS CSP process, a dam is built on CIS wafer surface to create a protective wall surrounding micro lens to keep it from contacting with glass wafer when bonded. The cover glass provides protection for the lens against harmful particles to deliver better illumination performance. The CIS wafer backside is then grinded to predetermined thickness in the next step before it goes through TSV process. The WLCSP process is completed with Backside RDL and ball mount process. Die saw, Pick & Place to chip tray, CP, and FT services are also available for convenient turkey total solutions.

An image sensor device can be combined with a processor device through the space-saving construction of a CIS CoW package. When building the CIS CoW package, the image sensor device first remains in its wafer form when TSV (through silicon via) and backside RDL (redistribution layer) are built onto the image sensor wafer followed by Cu/Ni/Au bump plating to create foundation for interconnection with the micro bumps (Cu/Ni/SnAg) on the single-chip form processor device. The package is completed with wafer level underfill and optional molding compound to provide further protection against stress for the chips inside.

  
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