3-Dimensional Integrated Circuit (3DIC) Packaging

Through-silicon Via (TSV) is an advanced 3D interconnection structure, which vertically passes through layers of silicon wafers or dies to connect stacked integrated circuits to complete the 3D chip fabrication. 3DIC architecture reduces energy consumption by cutting traveling distance for current while maximizing space for circuit designers and their limitless creativity. Our facilities are equipped with leading assembly lines to provide total solution of 3DIC packages.


MEOL Via Middle and Via Last

Advantages of TSV
• High Speed
• Low Power Consumption
• Small Form Factor
• Heterogeneous Integration

TSV Capability
• 6 um TSV diameter with 35 um die thickness
• Aspect ratio = 6 is achievable. (Via Middle > 10 )
• Less than 200 ℃ CVD oxide & Nitride
• Stop Layer can be Tungsten, Silicide
• Undercut less than 200 nm

BEOL Chip Stacking

3DIC offers high density packaging solutions for memory and logic devices. Back-of-the-line (BEOL) chip stacking allows more circuit space to enhance chip performance while maintaining a minimized, cost-effective package size

• Thin Die Dicing, Pick & Place – Si Thickness: 35 μm
• High Accuracy COC/COW Stacking – Accuracy: +/-3 μm
• Micro Bump Joint –Bump Size: 20 μm
• Narrow Gap Underfill – Min. Gap: 15 μm
• There is no die chipping or side wall crack issue on 35 um wafer thickness by Stealth Dicing.
• No die crack & poor joining after high accuracy TC bonding (± 3um).
• No under-fill void on 20 um stand off height.
• Under-fill fillet width can be controlled by Trimming process.

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