Innovative Technology
Panel Level Fan Out
Fan-out packaging is going to become the mainstream for high-end device application, especially for multi-die, heterogeneous integration for both active & passive devices. High density interconnect, excellent performance in electrical performance and power consumption can also be achieved by panel FO. PTI' Panel level FO packaging offers the merits of high production efficiency with better utilization & unit output in comparison to wafer level FO.
Panel Level Fan Out Solution
CHIEFS®
Chip First
- Cost effective than CLIP®
- AP, BB, ASIC, PMIC, memory
- Multi-die (dual/ triple die) in one PKG available
- Die backsdie would be exposed
- Min. RDL L/S ≥ 5/5um
CLIP®
Chip Last
- Known good RDL, avoid die loss
- Passive embedded available
- CPU, GPU, FPGA, thermal sensitive devices
- Multi-die (≥triple die) in one PKG available
- Min. RDL L/S ≥2/2um
PiFO®
Chip Middle
- Double side RDLs structure with e-plated Cu pillars as top/ bottom RDLs interconnection
- Passive integration available
- RF module, sensor, AP (PoPb), optical device, SiP….etc, 3D stacking application
- Min. RDL L/S ≥5/5um on die backside, and ≥2/2um on die front side
BF2O®
Bump Free
- No need wafer bumping
- For small I/O & few layer count & single die PKG
- PMIC, audio, PA
- Min. RDL L/S ≥15/15um
Higher Capability and Innovation Technology
- Panel level FO packaging offers higher production efficiency in comparison to wafer level FO packaging
- 4 types of package structures are available including Bump-free, Chip First, Chip Last & Chip Middle
- Multi-device including actives & passives for heterogeneous integration
- Fine pitch tall Cu pillar is available to enable vertical device integration
- High density interconnect is available by fine RDL L/S
- Low temp. cured dielectrics to fulfill varied device requirement including logic & memory
- Excellent engineering capability for design, process & failure analysis to have robust packaging
- Thermal, mechanical & electrical simulation capability to offer customer the best package design & BOM
- Turnkey FOPLP assembly & embedded die FO-RDL substrate are both available
Application
- Compatible for both logic & memory devices from low I/O to high-end requirements
- Wider application including power, RF, consumer electronics, mobile, storage, automotive, HPC & AiP
Feature
- System in package (SiP) is available to allow multi-die & passive component integration
- Fine RDL L/S & shortest signal transmission path to have good electrical performance
- Fine pitch e-plated tall Cu pillar is available for Fan-out PoP with varied devices
