3D IC is one kind of heterogeneous technology which is integrated vertically by Si wafers or chips. The interconnection is composed by u-bumps and Through Silicon Via (TSV). TSV fabrication is regarded as the heart of 3D IC because it provides the advantages of shortening the interconnection path, thinner package size, high function density, low power consumption, smaller form factor and high performance; these benefits make 3D IC get commercial success in some specific applications, such like HPC and AI.
High Performance, High Density and Low Power Consumption
Our solution in 3D IC offers Through Silicon Via (TSV) Via Last and memory cube die stacking.
- For Via Last (VL) process, IDM/Foundry will perform FEOL (CMOS) and metallization, and PTI proceeds u-bump, TSV formation, TSV fill, RDL (option); ie stacking and assembly processes (BEOL).
- For die stacking process, the interconnection of die (TSV, u-bump) is finished by MEOL process first, and then singulation is completed by BEOL process, the die stacking is further performed by thermal compression bonding (TCB).
- Good stability in TSV process (Lithography, Etching, CVD, Electroplating…)
- Excellent TTV control in wafer thinning
- Keep good uniformity control of u-bump height
- High yield and high accuracy die stacking
- Wafer level molding & molding grinding to achieve exposed die structure
- Laser grooving for LK / ELK u-controller chip
- High performance computing
- Artificial Intelligence
- High reliability Via-middle and Via-last process
- Various die stacking process, including chip-on-wafer and chip-on-substrate capability
- Double-sided u-bump formation process by well-controlled TTV
- Wafer level assembly (Wafer level molding, molding grinding, probing)
- Good control of package warpage (<=10um)
CMOS image sensor
CMOS Image Sensor (CIS) is an electronic device that converts an optical image into an analog signal. Basically, it can be divided into two categories, Frontside Illumination(FSI) and Backside Illumination (BSI). Both of them are widely utilized at several commercial demand recent years, such like camera sensor, mobile and automotive. Recently, the most attractive is stack-CIS, that BSI CIS, memory wafer and Image Signal Processor(ISP) wafer are vertically integrated and higher performance, lower power consumption would be the advantages for high-end application.
TSV Technology in CMOS Image Sensor
An image sensor device can be combined with a processor device through the space-saving construction of a CIS package. When building the CIS package, the image sensor device first remains in its wafer form when TSV (through silicon via) and backside RDL (redistribution layer) are built onto the image sensor wafer followed by bump plating to create foundation for interconnection with the micro bumps on the single-chip form processor device. The package is completed with wafer level underfill and optional molding compound to provide further protection against stress for the chips inside. PTI offers CIS (CMOS Image Sensor) TSV CSP with TSV interconnections. The profits of CIS TSV CSP are high-speed, compact package form factor and low CIS z-height. PTI has outstanding moisture-resistance material, good TSV related process of Via-last and excellent reliability performance.
- Excellent TSV process engineering capability
- Well-controlled electroplating for conformal Cu fill of TSV
- Line/Spacing of RDL capability: 5um / 5um
- Cost efficiency of Ball Drop process